In recent years, it has been attempted to form a semiconductor integrated circuit on an insulating substrate made of a glass or sapphire, because the parasitic capacitance between the substrate and the conductive interconnections is reduced, thus improving the operating speed. Especially, where glass materials such as quartz are used, no limitations are imposed on the size of the substrate, unlike silicon wafers. Also, glass materials are inexpensive. In addition, it is easy to provide isolation between devices. Furthermore, latchup which presents problems in the case of CMOS monolithic integrated circuits does not take place. These reasons apart, it is necessary to integrate semiconductor devices with liquid crystal devices (elements) or photosensitive devices (elements) in the case of a liquid crystal display or intimate contact type image sensor. Therefore, thin-film transistors (TFTs) are required to be formed on a transparent plate or substrate.
For these reasons, thin-film semiconductor devices have been fabricated on an insulating substrate. However, the conventional thin-film semiconductor devices are fabricated by the same manufacturing steps as are used to form a semiconductor integrated circuit, or a monolithic integrated circuit, on a semiconductor substrate and, therefore, a quite large number of masks are required for the fabrication. In the conventional monolithic integrated circuit, a single crystal of silicon forming the substrate is quite excellent in reliability and hardly suffers from deformation due to thermal treatment or other problems. Consequently, alignment error rarely occurs in mask alignment steps.
However, generally commercially available insulating substrates are inferior in reliability to silicon substrates. Especially, substrates made of glasses are deformed unpredictably by thermal treatment and so the designed masks fail to fit the substrates. In this way, mask alignment steps are sometimes very difficult to carry out.
Where a liquid crystal display or the like is fabricated, it is necessary to fabricate an integrated circuit in a much larger area than the prior art integrated circuit. This further complicates the mask alignment steps. Accordingly, there is a demand for a reduction in the number of mask alignment steps.